View LTC1290DI_841608.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc1290 single chip 12-bit data acquisition system 12-bit 8-channel sampling data acquisition system ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd ltc1290 differential input (+) 5v common mode range (? 1k single-ended input 0v to 5v or 5v 15v overvoltage range* to and from microprocessor 0.1 f 1n5817 ?v 22 f tantalum 1n5817 1n4148 4.7 f tantalum 1 f lt 1027 5v 8v to 40v * for overvoltage protection on only one channel limit the input current to 15ma. for overvoltage protection on more than one channel limit the input current to 7ma per channel and 28ma for all channels. (see section on overvoltage protection in the applications information section.) conversion results are not valid when the selected or any other channel is overvoltaged (v in < v or v in > v cc ). 1290 ?ta01 + + s f ea t u re d u escriptio the ltc ? 1290 is a data acquisition component which contains a serial i/o successive approximation a/d con- verter. it uses ltcmos tm switched capacitor technology to perform either 12-bit unipolar or 11-bit plus sign bipolar a/d conversions. the 8-channel input multiplexer can be configured for either single-ended or differential inputs (or combinations thereof). an on-chip sample-and-hold is included for all single-ended input channels. when the ltc1290 is idle it can be powered down with a serial word in applications where low power consumption is desired. the serial i/o is designed to be compatible with industry standard full duplex serial interfaces. it allows either msb- or lsb-first data and automatically provides 2's comple- ment output coding in the bipolar mode. the output data word can be programmed for a length of 8, 12 or 16 bits. this allows easy interface to shift registers and a variety of processors. ltcmos is a trademark of linear technology corporation. key specificatio s u n software programmable features C unipolar/bipolar conversion C four differential/eight single-ended inputs C msb- or lsb-first data sequence C variable data word length C power shutdown n built-in sample-and-hold n single supply 5v or 5v operation n direct four-wire interface to most mpu serial ports and all mpu parallel ports n 50khz maximum throughput rate n resolution: 12 bits n fast conversion time: 13 m s max over temp n low supply current: 6.0ma u a o pp l ic at i ty p i ca l , ltc and lt are registered trademarks of linear technology corporation.
2 ltc1290 ltc1290b ltc1290c ltc1290d parameter conditions min typ max min typ max min typ max units offset error (note 4) l 1.5 1.5 1.5 lsb linearity error (inl) (notes 4,5) l 0.5 0.5 0.75 lsb gain error (note 4) l 0.5 1.0 4.0 lsb minimum resolution for which l 12 12 12 bits no missing codes are guaranteed analog and ref input range (note 7) (v C ) C 0.05v to v cc + 0.05v (v C ) C 0.05v to v cc + 0.05v (v C ) C 0.05v to v cc + 0.05v v on channel leakage current on channel = 5v l 1 1 1 m a (note 8) off channel = 0v on channel = 0v l 1 1 1 m a off channel = 5v off channel leakage current on channel = 5v l 1 1 1 m a (note 8) off channel = 0v on channel = 0v l 1 1 1 m a off channel = 5v a u g w a w u w a r b s o lu t exi t i s supply voltage (v cc ) to gnd or v C ........................ 12v negative supply voltage (v C ) .................... C 6v to gnd voltage analog/reference inputs ......... (v C ) C 0.3v to v cc + 0.3v digital inputs ........................................ C 0.3v to 12v digital outputs ........................... C 0.3v to v cc + 0.3v power dissipation ............................................. 500mw (notes 1, 2) operating temperature range ltc1290bc, ltc1290cc, ltc1290dc .... 0 c to 70 c ltc1290bi, ltc1290ci, LTC1290DI .... C 40 c to 85 c ltc1290bm, ltc1290cm, ltc1290dm ....................................... C 55 c to 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec.)................ 300 c wu u package / o rder i for atio ltc1290bcsw ltc1290ccsw ltc1290dcsw ltc1290bisw ltc1290cisw LTC1290DIsw co verter a d ultiplexer characteristics uu w (note 3) 1 2 3 4 5 6 7 8 9 10 top view j package 20-lead ceramic dip n package 20-lead pdip 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd t jmax = 150 c, q ja = 80 c/w (j) t jmax = 110 c, q ja = 100 c/w (n) t jmax = 110 c, q ja = 130 c/w (sw) order part number order part number ltc1290bmj ltc1290cmj ltc1290dmj ltc1290bij ltc1290cij LTC1290DIj ltc1290bin ltc1290cin LTC1290DIn ltc1290bcn ltc1290ccn ltc1290dcn 1 2 3 4 5 6 7 8 9 10 top view sw package 20-lead plastic so wide 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd
3 ltc1290 ltc1290b/ltc1290c/ltc1290d symbol parameter conditions min typ max units f sclk shift clock frequency v cc = 5v (note 6) 0 2.0 mhz f aclk a/d clock frequency v cc = 5v (note 6) (note 10) 4.0 mhz t acc delay time from cs to d out data valid (note 9) 2 aclk cycles t smpl analog input sample time see operating sequence 7 sclk cycles t conv conversion time see operating sequence 52 aclk cycles t cyc total cycle time see operating sequence (note 6) 12 sclk + cycles 56 aclk t ddo delay time, sclk to d out data valid see test circuits ltc1290bc, ltc1290cc l 130 220 ns ltc1290dc, ltc1290bi ltc1290ci, LTC1290DI ltc1290bm, ltc1290cm l 180 270 ns ltc1290dm t dis delay time, cs - to d out hi-z see test circuits l 70 100 ns t en delay time, 2nd aclk to d out enabled see test circuits l 130 200 ns t hcs hold time, cs after last sclk v cc = 5v (note 6) 0 ns t hdi hold time, d in after sclk - v cc = 5v (note 6) 50 ns t hdo time output data remains valid after sclk 50 ns t f d out fall time see test circuits l 65 130 ns t r d out rise time see test circuits l 25 50 ns t sudi setup time, d in stable before sclk - v cc = 5v (note 6) 50 ns t sucs setup time, cs before clocking in (notes 6, 9) 2 aclk cycles first address bit + 100ns t whcs cs high time during conversion v cc = 5v (note 6) 52 aclk cycles c in input capacitance analog inputs on channel 100 pf analog inputs off channel 5 pf digital inputs 5 pf (note 3) ac characteristics e lectr ic al c c hara ter st ics digital a d u i dc (note 3) ltc1290b/ltc1290c/ltc1290d symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2.0 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 4.75v i o = 10 m a 4.7 v i o = 360 m a l 2.4 4.0 v v ol low level output voltage v cc = 4.75v i o = 1.6ma l 0.4 v i oz high-z output leakage v out = v cc , cs high l 3 m a v out = 0v, cs high l C3 m a i source output source current v out = 0v C20 ma
4 ltc1290 ltc1290b/ltc1290c/ltc1290d symbol parameter conditions min typ max units i sink output sink current v out = v cc 20 ma i cc positive supply current cs high l 612 ma cs high ltc1290bc, ltc1290cc l 510 m a power shutdown ltc1290dc, ltc1290bi aclk off ltc1290ci, LTC1290DI ltc1290bm, ltc1290cm l 515 m a ltc1290dm i ref reference current v ref = 5v l 10 50 m a i C negative supply current cs high l 150 m a e lectr ic al c c hara ter st ics digital a d u i dc (note 3) below v C or one diode drop above v cc . be careful during testing at low v cc levels (4.5v), as high level reference or analog inputs (5v) can cause this input diode to conduct, especially at elevated temperatures and cause errors for inputs near full scale. this spec allows 50mv forward bias of either diode. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. to achieve an absolute 0v to 5v input voltage range will therefore require a minimum supply voltage of 4.950v over initial tolerance, temperature variations and loading. note 8: channel leakage current is measured after the channel selection. note 9: to minimize errors caused by noise at the chip select input, the internal circuitry waits for two aclk falling edge after a chip select falling edge is detected before responding to control input signals. therefore, no attempt should be made to clock an address in or data out until the minimum chip select setup time has elapsed. note 10: increased leakage currents at elevated temperatures cause the s/h to droop, therefore it's recommended that f aclk 3 500khz at 125 c, f aclk 3 125khz at 85 c and f aclk 3 15khz at 25 c. the l denotes specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd, agnd and ref C wired together (unless otherwise noted). note 3: v cc = 5v, v ref + = 5v, v ref C = 0v, v C = 0v for unipolar mode and C 5v for bipolar mode, aclk = 4.0mhz unless otherwise speicfied. note 4: these specs apply for both unipolar and bipolar modes. in bipolar mode, one lsb is equal to the bipolar input span (2v ref ) divided by 4096. for example, when v ref = 5v, 1lsb (bipolar) = 2(5v)/4096 = 2.44mv. note 5: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: recommended operating conditions. note 7: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop cc hara terist ics uw a t y p i ca lper f o r c e supply current vs temperature supply current vs supply voltage unadjusted offset voltage vs reference voltage supply voltage, v cc (v) 46810 supply current, i cc (ma) 1290 ?tpc01 26 22 18 14 10 6 2 aclk = 4mhz t a = 25 c ambient temperature, t a ( c) ?0 supply current, i cc (ma) 30 10 9 8 7 6 5 4 3 lt1290 ?tpc02 ?0 70 ?0 50 10 90 110 130 aclk = 4mhz v cc = 5v reference voltage, v ref (v) 1 offset error (lsb = ?v ref ) 5 1290 ?tpc03 2 3 4 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 1 4096 v os = 0.25mv v os = 0.125mv v cc = 5v
5 ltc1290 cc hara terist ics uw a t y p i ca lper f o r c e change in offset vs temperature change in linearity vs reference voltage reference voltage, v ref (v) 0 linearity error (lsb = ?v ref ) 1.25 1.00 0.75 0.50 0.25 0 4 1290 ?tpc04 1 2 3 5 1 4096 v cc = 5v change in gain vs reference voltage reference voltage, v ref (v) 1 change in gain error (lsb = ?v ref ) 0.2 ?.1 0 5 1290 ?tpc05 0.3 0.4 0.5 2 3 4 1 4096 v cc = 5v ambient temperature, t a ( c) ?0 magnitude of offset change ? ? offset ? (lsb) 0.5 0.4 0.3 0.2 0.1 0 ?0 30 50 130 1290 ?tpc06 ?0 10 70 90 110 aclk = 4mhz v cc = 5v v ref = 5v change in gain error vs temperature ambient temperature, t a ( c) ?0 magnitude of gain change ? ? gain ? (lsb) 0.5 0.4 0.3 0.2 0.1 0 ?0 30 50 130 1290 ?tpc08 ?0 10 70 90 110 aclk = 4mhz v cc = 5v v ref = 5v change in linearity error vs temperature ambient temperature, t a ( c) ?0 0 magnitude of linearity change ? ? linearity ? (lsb) 0.1 0.3 0.4 0.5 ?0 30 50 130 1290 ?tpc07 0.2 ?0 10 70 90 110 0.6 aclk = 4mhz v cc = 5v v ref = 5v maximum filter resistor vs cycle time maximum aclk frequency vs source resistance r source ( w ) 100 0 maximum aclk frequency* (mhz) 4 5 1k 10 k 100k 1290 ?tpc09 3 2 1 v cc = 5v v ref = 5v t a = 25 c + input input v in r source * maximum aclk frequency represents the aclk frequency at which a 0.1lsb shift in the error at any code transition from its 4mhz value is first detected. cycle time, t cyc ( m s) maximum r filter ** ( w ) 10 100 1k 10k 10 1000 10000 1290 ?tpc10 1.0 100 + v in c filter 3 1 m f r filter ** maximum r filter represents the filter resistor value at which a 0.1lsb change in full-scale error from its value at r filter = 0 is first detected.
6 ltc1290 cc hara terist ics uw a t y p i ca lper f o r c e sample-and-hold acquisition time vs source resistance r source + ( w ) 100 1 s & h aquisition time to 0.02% ( m s) 10 100 1k 10k ltc1290 ?tpc11 + v in r source + v ref = 5v v cc = 5v t a = 25 c 0v to 5v input step aclk frequency (mhz) 0 supply current, i cc ( a) 1.00 2.00 3.00 4.00 1290 ?tpc13 200 180 160 140 120 100 80 60 40 20 v cc = 5v cmos levels supply current (power shutdown) vs aclk supply current (power shutdown) vs temperature ambient temperature, t a ( c) ?0 supply current, i cc ( a) 10 9 8 7 6 5 4 3 2 1 0 ?0 30 50 130 1290 ?tpc12 ?0 10 70 90 110 aclk off during power shutdown input channel leakage current vs temperature ambient temperature, t a ( c) ?0 0 input channel leakage current (na) 100 300 400 500 1000 700 ?0 30 50 130 1290 ?tpc14 200 800 900 600 ?0 10 70 90 110 on channel off channel guaranteed noise error vs reference voltage reference voltage, v ref (v) 0 0 peak-to-peak noise error (lsbs) 0.25 0.75 1.00 1.25 2 4 5 2.25 1290 ?tpc15 0.50 13 1.50 1.75 2.00 ltc1290 noise 200 v p-p pi fu ctio s u uu ch0 to ch7 (pin 1 to pin 8): analog inputs. the analog inputs must be free of noise with respect to agnd. com (pin 9): common. the common pin defines the zero reference point for all single-ended inputs. it must be free of noise and is usually tied to the analog ground plane. dgnd (pin 10): digital ground. this is the ground for the internal logic. tie to the ground plane. agnd (pin 11): analog ground. agnd should be tied directly to the analog ground plane. v C (pin 12): negative supply. tie v C to most negative potential in the circuit. (ground in single supply applica- tions.) ref C , ref + (pins 13, 14): reference inputs. the refer- ence inputs must be kept free of noise with respect to agnd. cs (pin 15): chip select input. a logic low on this input enables data transfer. d out (pin 16): digital data output. the a/d conversion result is shifted out of this output.
7 ltc1290 pi fu ctio s u uu d in (pin 17): digital data input. the a/d configuration word is shifted into this input after cs is recognized. sclk (pin 18): shift clock. this clock synchronizes the serial data transfer. aclk (pin 19): a/d conversion clock. this clock controls the a/d conversion process. v cc (pin 20): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. block diagram input shift register sample- and- hold 12-bit capacitive dac v cc 20 analog input mux 1 2 3 4 5 6 7 8 9 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com d out 16 sclk 18 control and timing 15 cs ltc1290 ?bd 17 ref + 14 dgnd 10 agnd 11 v 12 ref 13 comp output shift register d in 19 aclk 12-bit sar test circuits 5v a a i off i on polarity off channels on channel ltc1290 ?tc01 on and off channel leakage current load circuit for t dis and t en d out 3k 100pf test point 5v waveform 2 waveform 1 ltc1290 ?tc02
8 ltc1290 test circuits voltage waveforms for d out delay time, t ddo load circuit for t ddo , t r and t f voltage waveform for d out rise and fall times, t r , t f voltage waveforms for t en and t dis d out 1.4v 3k 100pf test point 1290 ?tc05 sclk d out 0.8v t ddo 0.4v 2.4v ltc1290 ?tc03 d out 0.4v 2.4v t r t f ltc1290 ?tc04 d out waveform 1 (see note 1) t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control . note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. ltc1290 ?tc06 t en 2.4v 0.8v aclk 12 2.0v
9 ltc1290 u s a o pp l ic at i wu u i for atio of the data exchange the requested conversion begins and cs should be brought high. after t conv , the conversion is complete and the results will be available on the next data transfer cycle. as shown below, the result of a conversion is delayed by one cs cycle from the input word requesting it. the ltc1290 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive a/d converter 2. analog multiplexer (mux) 3. sample-and-hold (s/h) 4. synchronous, full duplex serial interface 5. control and timing logic digital considerations serial interface the ltc1290 communicates with microprocessors and other external circuitry via a synchronous, full duplex, four-wire serial interface (see operating sequence). the shift clock (sclk) synchronizes the data transfer with each bit being transmitted on the falling sclk edge and captured on the rising sclk edge in both transmitting and receiving systems. the data is transmitted and received simultaneously (full duplex). data transfer is initiated by a falling chip select (cs) signal. after the falling cs is recognized, an 8-bit input word is shifted into the d in input which configures the ltc1290 for the next conversion. simultaneously, the result of the previous conversion is output on the d out line. at the end sgl/ diff select 1 select 0 uni msbf wl1 mux address msb-first/ lsb-first unipolar/ bipolar word length ltc1290 ?ai02 odd/ sign wl0 d in d out d out word 0 d in word 1 data transfer d out word 2 d in word 3 d out word 1 d in word 2 data transfer t conv a/d conversion t conv a/d conversion ltc1290 ?ai01 input data word the ltc1290 8-bit data word is clocked into the d in input on the first eight rising sclk edges after chip select is recognized. further inputs on the d in pin are then ignored until the next cs cycle. the eight bits of the input word are defined as follows: 123456789101112 t conv t cyc shift configuration word in t smpl shift a/d result out and new configuration word in b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (sb) ltc1290 ?ai03 sclk d in d out cs don? care dont care operating sequence (example: differential inputs (ch3-ch2), bipolar, msb-first and 12-bit word length)
10 ltc1290 u s a o pp l ic at i wu u i for atio mux address the first four bits of the input word assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of table 1. note that in differential mux address differential channel selection table 1. multiplexer channel selection mux address sgl/ diff select 1 0 odd sign 10 00 + C 10 01 + C 10 10 + C 10 11 + C 11 00 + C 11 01 + C 11 10 + C 11 11 + C sgl/ diff odd sign select 1 0 00 00+C 00 01 +C 00 10 +C 00 11 + C 01 00C+ 01 01 C+ 01 10 C+ 01 11 C + 0 1 23 4 56 7 0 1 2 3 4 5 6 7 com single-ended channel selection mode (sgl/diff = 0) measurements are limited to four adjacent input pairs with either polarity. in single-ended mode, all input channels are measured with respect to com. figure 1. examples of multiplexer options on the ltc1290 0 1 2 3 4 5 6 7 channel com ( ) 8 single-ended + + + + + + + 0,1 channel 4 differential 2,3 4,5 6,7 + ( ) + + ( ) + ( ) + ( ) ( + ) ( + ) ( + ) ( + ) 4 5 6 7 channel com ( ) combinations of differential and single-ended + + + + + + 0,1 2,3 com (unused) changing the mux assignment ?n the fly com ( ) 4,5 6,7 5,4 1st conversion 2nd conversion + + + + + 7 6 { { { { { { { { { { ltc1290 ?f01
11 ltc1290 u s a o pp l ic at i wu u i for atio unipolar/bipolar (uni) the fifth input bit (uni) determines whether the conver- sion will be unipolar or bipolar. when uni is a logical one, a unipolar conversion will be performed on the selected unipolar transfer curve (uni = 1) input voltage. when uni is a logical zero, a bipolar conver- sion will result. the input span and code assignment for each conversion type are shown in the figures below. unipolar output code (uni = 1) bipolar transfer curve (uni = 0) bipolar output code (uni = 0) 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ltc1290 ai04b output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v input voltage (v ref = 5v) 4.9988v 4.9976v 0.0012v 0v ltc1290 ?ai04a output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 input voltage ?lsb ?lsb ?v ref ) + 1lsb ?(v ref ) input voltage (v ref = 5v) 0.0024v 0.0048v ?.9976v ?.0000v output code 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v input voltage (v ref = 5v) 4.9976v 4.9851v 0.0024v 0v ltc1290 ai05a 1lsb v ref ?2lsb v ref ?1lsb v ref v in 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 ?lsb ?lsb ? ref ? ref + 1lsb ltc1290 ai05b
12 ltc1290 u s a o pp l ic at i wu u i for atio msb-first/lsb-first format (msbf) the output data of the ltc1290 is programmed for msb- first or lsb-first sequence using the msbf bit. for msb first output data the input word clocked to the ltc1290 should always contain a logical one in the sixth bit location (msbf bit). likewise for lsb-first output data the input word clocked to the ltc1290 should always contain a zero in the msbf bit location. the msbf bit affects only the order of the output data word. the order of the input word is unaffected by this bit. msbf output format 0 lsb first 1 msb first word length (wl1, wl0) and power shutdown the last two bits of the input word (wl1 and wl0) program the output data word length and the power shutdown feature of the ltc1290. word lengths of 8, 12 or 16 bits can be selected according to the following table. the wl1 and wl0 bits in a given d in word control the length of the present, not the next, d out word. wl1 and wl0 are never dont cares and must be set for the correct d out word length even when a dummy d in word is sent. on any transfer cycle, the word length should be made equal to the number of sclk cycles sent by the mpu. power down will occur when wl1 = 0 and wl0 = 1 is selected. the previous conversion result will be clocked out as a 10 bit word so a dummyconversion is required before powering down the ltc1290. conversions are resumed once cs goes low or an sclk is applied, if cs is already low. wl1 wl0 output word length 0 0 8-bits 0 1 power shutdown 1 0 12-bits 1 1 16-bits deglitcher a deglitching circuit has been added to the chip select input of the ltc1290 to minimize the effects of errors caused by noise on that input. this circuit ignores changes in state on the cs input that are shorter in duration than one aclk cycle. after a change of state on the cs input, the ltc1290 waits for two falling edge of the aclk before recognizing a valid chip select. one indication of cs recognition is the d out line becoming active (leaving the hi-z state). note that the deglitching applies to both the rising and falling cs edges. cs low during conversion in the normal mode of operation, cs is brought high during the conversion time. the serial port ignores any sclk activity while cs is high. the ltc1290 will also operate with cs low during the conversion. in this mode, sclk must remain low during the conversion as shown in the following figure. after the conversion is complete, the d out line will become active with the first output bit. then the data transfer can begin as normal. low cs recognized internally high cs recognized internally d out cs ltc1290 ?ai07 aclk valid output hi-z d out cs ltc1290 ?ai06 aclk valid output hi-z
13 ltc1290 u s a o pp l ic at i wu u i for atio figure 2. data output (d out ) timing with different word lengths t smpl b11 18 t conv b10 b9 b8 b7 b4 (sb) 8-bit word length sclk cs d out lsb-first t smpl b11 1 t conv (sb) 12-bit word length sclk cs d out lsb-first 10 12 d out msb-first d out msb-first (sb) t smpl 1 t conv 16-bit word length 12 16 fill zeros * ** * in unipolar mode, these bits are filled with zeros. in bipolar mode, the sign bit is extended into these locations. ltc1290 f02 b6 b5 b0 b1 b2 b3 b4 b7 b5 b6 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 sclk cs d out lsb-first d out msb-first b11 (sb) (sb) b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 the last four bits are truncated
14 ltc1290 u s a o pp l ic at i wu u i for atio microprocessor interfaces the ltc1290 can interface directly (without external hard- ware) to most popular microprocessor (mpu) synchro- nous serial formats (see table 2). if an mpu without a serial interface is used, then four of the mpus parallel port lines can be programmed to form the serial link to the ltc1290. included here are two serial interface examples and one example showing a parallel port programmed to form the serial interface serial port microprocessors most synchronous serial formats contain a shift clock (sclk) and two data lines, one for transmitting and one for receiving. in most cases data bits are transmitted on the falling edge of the clock (sclk) and captured on the rising edge. however, serial port formats vary among mpu manufactures as to the smallest number of bits that can be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers). they also vary as to the order in which the bits are transmitted (lsb or msb first). the following examples show how the ltc1290 accommodates these differences. figure 4. cs low during conversion (cs must go high to low once to insure proper operation in this mode) b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 shift result out and new address in sclk cs d out d in t smpl sample analog input shift mux address in ltc1290 f04 48 to 52 aclk cyc sclk must remain low don? care figure 3. cs high during conversion b11b10b9b8b7b6b5b4b3b2b1b0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 shift result out and new address in sclk cs d out d in t smpl sample analog input shift mux address in ltc1290 f03 48 to 52 aclk cyc don? care
15 ltc1290 u s a o pp l ic at i wu u i for atio microwire and microwire plus are trademarks of national semiconductor corp ltc1290 ?ai08 sclk d out ltc1290 cs analog inputs go sk si cop402 d in so b6 b5 b4 b7 first 4 bits second 4 bits b10 b9 b8 b11 d out from ltc1290 stored in cop402 ram msb ? location $13 location $14 b2 b1 b0 b3 third 4 bits lsb location $15 ? b11 is msb in unipolar or sign bit in bipolar national microwire (cop402) the cop402 transfers data msb first and in 4-bit incre- ments (nibbles). this is easily accommodated by setting the ltc1290 to msb-first format and 12-bit word length. the data output word is then received by the cop402 in three 4-bit blocks. cop402 code mnemonic comments clra must be first instruction lbi 1,0 br = 1bd = 0 initialize b reg. stii 8 first d in nibble in $10 stii e second d in nibble in $11 stii 0 null data in $12, b = $13 lei c set en to (1100) bin loop sc carry set ldd 1,0 load first d in nibble in acc ogi 0 go (cs) cleared xas acc to shift reg. begin shift ldd 1,1 load next d in nibble in acc nop timing xas next nibble, shift continues xis 0 first nibble d out to $13 ldd 1,2 put null data in acc xas shift continues, d out to acc xis 0 next nibble d out to $14 rc clear carry clra clear acc xas third nibble d out to acc ogi 1 go (cs) set xis 0 third nibble d out to $15 lbi 1,3 set b reg. for next loop motorola spi (mc68hc05c4) the mc68hc05c4 transfers data msb first and in 8-bit increments. programming the ltc1290 for msb-first format and 16-bit word length allows the 12-bit data output to be received by the mpu as two 8-bit bytes with the final four unused bits filled with zeros by the ltc1290. hardware and software interface to cop402 processor table 2. microprocessors with hardware serial interfaces compatible with the ltc1290** part number type of interface motorola mc6805s2, s3 spi mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi hitachi hd6305 sci synchronous hd6301 sci synchronous hd63701 sci synchronous hd6303 sci synchronous hd64180 sci synchronous national semiconductor cop400 family microwire tm cop800 family microwire/plus tm ns8050u microwire/plus hpc16000 family microwire/plus texas instruments tms7002 serial port tms7042 serial port tms70c02 serial port tms70c42 serial port tms32011* serial port tms32020 serial port tms370c050 spi *requires external hardware ** contact factory for interface information for processors not on this list
16 ltc1290 u s a o pp l ic at i wu u i for atio hardware and software interface to motorola mc68hc05c4 processor ltc1290 ?ai09 sclk d out ltc1290 cs analog inputs co sck miso mc68hc05c4 d in mosi byte 1 b10 b9 b8 b11 b6 b5 b4 b7 d out from ltc1290 stored in mc68hc05c4 ram msb* location $61 byte 2 b2 b1 b0 b3 0 0 0 0 lsb location $62 *b11 is msb in unipolar or sign bit in bipolar mc68hc05c4 code mnemonic comments lda #$50 configuration data for spcr sta $0a load data into spcr ($0a) lda #$ff config. data for port c ddr sta $06 load data into port c ddr lda #$0f load ltc1290 d in data into acc sta $50 load ltc1290 d in data into $50 start bclr 0,$20 co goes low (cs goes low) lda $50 load d in into acc from $50 sta $0c load d in into spi, start sck nop 8 nops for timing lda $0b check spi status reg lda $0c load ltc1290 msbs into acc sta $61 store msbs in $61 sta $0c start next spi cycle nop 6 nops for timing bset 0,$02 co goes high (cs goes high) lda $0b check spi status register lda $0c load ltc1290 lsbs into acc sta $62 store lsbs in $62 parallel port microprocessors when interfacing the ltc1290 to an mpu which has a parallel port, the serial signals are created on the port with software. three mpu port lines are programmed to create the cs, sclk and d in signals for the ltc1290. a fourth port line reads the d out line. an example is made of the intel 8051/8052/80c252 family. intel 8051 to interface to the 8051, the ltc1290 is programmed for msb-first format and 12-bit word length. the 8051 gener- ates cs, sclk and d in on three port lines and reads d out on the fourth. hardware and software interface to intel 8051 processor ltc1290 ?ai10 d in cs aclk ltc1290 d out analog inputs p1.1 p1.2 p1.4 ale 8051 sclk p1.3 b10 b9 b8 b11 b6 b5 54 b7 d out from ltc1290 stored in 8051 ram msb* r2 b2 b1 b0 b3 0 0 0 0 lsb r3 *b11 is msb in unipolar or sign bit in bipolar
17 ltc1290 u s a o pp l ic at i wu u i for atio 8051 code mnemonic comments mov p1,#02h bit 1 port 1 set as input clr p1.3 sclk goes low setb p1.4 cs goes high cont mov a,#0eh d in word for ltc1290 clr p1.4 cs goes low mov r4,#08h load counter nop delay for deglitcher loop mov c,p1.1 read data bit into carry rlc a rotate data bit into acc mov p1.2,c output d in bit to ltc1290 setb p1.3 sclk goes high clr p1.3 sclk goes low djnz r4,loop next bit mov r2,a store msbs in r2 mov c,p1.1 read data bit into carry clr a clear acc rlc a rotate data bit into acc setb p1.3 sclk goes high clr p1.3 sclk goes low mov c,p1.1 read data bit into carry rlc a rotate data bit into acc setb p1.3 sclk goes high clr p1.3 sclk goes low mov c,p1.1 read data bit into carry rlc a rotate data bit into acc setb p1.3 sclk goes high clr p1.3 sclk goes low mov c, p1.1 read data bit into carry rrc a rotate right into acc rrc a rotate right into acc rrc a rotate right into acc rrc a rotate right into acc mov r3,a store lsbs in r3 setb p1.3 sclk goes high clr p1.3 sclk goes low setb p1.4 cs goes high mov r5,#0bh load counter delay djnz r5,delay go to delay if not done 8 channels 8 channels 8 channels 3 3 3 3 3-wire serial interface to other peripherals or ltc1290s 2 10 output port serial data mpu ltc1290 f05 ltc1290 cs ltc1290 cs ltc1290 cs sharing the serial interface the ltc1290 can share the same 3-wire serial interface with other perpheral components or other ltc1290s (see figure 5). in this case, the cs signals decide which ltc1290 is being addressed by the mpu. analog considerations 1. grounding the ltc1290 should be used with an analog ground plane and single point grounding techniques. agnd (pin 11) should be tied directly to this ground plane. dgnd (pin 10) can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself. v cc (pin 20) should be bypassed to the ground plane with a 22 m f tantalum with leads as short as possible. v C (pin 12) should be bypassed with a 0.1 m f ceramic disk. for single supply applications, v C can be tied to the ground plane. it is also recommended that ref C (pin 13) and com (pin 9) be tied directly to the ground plane. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. figure 5. several ltc1290s sharing one 3-wire serial interface
18 ltc1290 u s a o pp l ic at i wu u i for atio v 22 m f tantalum v cc ltc1290 f06 0.1 f ceramic disk analog ground plane 1 10 20 figure 6. example ground plane for the ltc1290 figure 6 shows an example of an ideal ground plane design for a two-sided board. of course, this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 2. bypassing for good performance, v cc must be free of noise and ripple. any changes in the v cc voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code. v cc noise and ripple can be kept below 0.5mv by bypassing the v cc pin directly to the analog ground plane with a 22 m f tantalum capacitor and leads as short as possible. the lead from the device to the v cc supply should also be kept to a minimum and the v cc supply should have a low output impedance such as that obtained from a voltage regulator (e.g., lt323a). figures 7 and 8 show the effects of good and poor v cc bypassing. 3. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1290 have capacitive switching input current spikes. these current figure 7. poor v cc bypassing. noise and ripple can cause a/d errors vertical: 0.5mv/div horizontal: 10 m s/div cs v cc figure 8. good v cc bypassing keeps noise and ripple on v cc below 1mv horizontal: 10 m s/div vertical: 0.5mv/div spikes settle quickly and do not cause a problem. how- ever, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle com- pletely before the conversion begins. source resistance the analog inputs of the ltc1290 look like a 100pf capacitor (c in ) in series with a 500 w resistor (r on ) as shown in figure 9. c in gets switched between the selected + and C inputs once during each conversion cycle. large external source resistors and capacitances will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within the allowed time.
19 ltc1290 u s a o pp l ic at i wu u i for atio 4th sclk r on = 500 w last sclk c in = 100pf ltc1290 ? input r source + v in + c1 input r source v in c2 ltc1290 f09 figure 9. analog input equivalent circuit + input settling this input capacitor is switched onto the + input during the sample phase (t smpl , see figure 10). the sample phase starts at the 4th sclk cycle and lasts until the falling edge of the last sclk (the 8th, 12th or 16th sclk cycle depending on the selected word length). the voltage on the + input must settle completely within this sample time. minimizing r source + and c1 will improve the input settling time. if large + input source resistance must be used, the sample time can be increased by using a slower sclk frequency or selecting a longer word length. with the minimum possible sample time of 2 m s, r source + < 1k and c1 < 20pf will provide adequate settling . C input settling at the end of the sample phase the input capacitor switches to the C input and the conversion starts (see figure 10). during the conversion, the + input voltage is effectively held by the sample-and-hold and will not affect the conversion result. however, it is critical that the C input voltage be free of noise and settle completely during the first four aclk cycles of the conversion time. minimizing r source C and c2 will improve settling time. if large C input source resistance must be used, the time allowed for settling can be extended by using a slower aclk fre- quency. at the maximum aclk rate of 4mhz, r source C < 250 w and c2 < 20pf will provide adequate settling. input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 10). again, the + and C input sampling times can be extended as described above to accommo- date slower op amps. most op amps including the lt1006 and lt1013 single supply op amps can be made to settle well even with the minimum settling windows of 2 m s (+ input) and 1 m s (C input) which occur at the maximum sclk cs ??input aclk 1290 ?f10 1234 ?? ?? ?? mux address shifted in t smpl last sclk (8th, 12th or 16th depending on word length) 1 234 1st bit test ?input must settle during this time sample hold ??input must settle during this time ?input ?? figure 10. + and C input settling windows
20 ltc1290 u s a o pp l ic at i wu u i for atio clock rates (aclk = 4mhz and sclk = 2mhz). figures 11 and 12 show examples of adequate and poor op amp settling. horizontal: 500ns/div figure 11. adequate settling of op amps driving analog input vertical: 5mv/div horizontal: 20 m s/div figure 12. poor op amp settling can cause a/d errors vertical: 5mv/div rc input filtering it is possible to filter the inputs with an rc network as shown in figure 13. for large values of c f (e.g., 1 m f), the capacitive input switching currents are averaged into a net dc current. therefore, a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approximately i dc = (100pf)(v in /t cyc ) and is roughly proportional to v in . when running at the minimum cycle time of 20 m s, the input current equals 25 m a at v in = 5v. in this case, a filter resistor of 5 w will cause 0.1lsb of full-scale error. if a larger filter resistor must be used, errors can be eliminated by increas- ing the cycle time as shown in the typical curve of maximum filter resistor vs cycle time. figure 13. rc input filtering r filter v in c filter ltc1290 f13 ltc1290 "+" "? i dc input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input leakage specification of 1 m a (at 125 c) flowing through a source resistance of 1k w will cause a voltage drop of 1mv or 0.8lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see the typical curve of input channel leakage current vs tem- perature). noise coupling into inputs high source resistance input signals (>500 w ) are more sensitive to coupling from external sources. it is prefer- able to use channels near the center of the package (i.e., ch2 to ch7) for signals which have the highest output resistance because they are essentially shielded by the pins on the package ends (dgnd and ch0). grounding any unused inputs (especially the end pin, ch0) will also reduce outside coupling into high source resistances. 4. sample-and-hold single-ended inputs the ltc1290 provides a built-in sample-and-hold (s&h) function for all signals acquired in the single-ended mode (com pin grounded). this sample-and-hold allows the ltc1290 to convert rapidly varying signals (see the typical curve of s&h acquisition time vs source resistance). the input voltage is sampled during the t smpl time as shown in figure 10. the sampling interval begins after the fourth mux address bit is shifted in and continues during the remainder of the data transfer. on the falling edge of the final sclk, the s&h goes into hold mode and the conversion begins. the voltage will be held on either the 8th, 12th or 16th falling edge of the sclk depending on the word length selected.
21 ltc1290 u s a o pp l ic at i wu u i for atio differential inputs with differential inputs or when the com pin is not tied to ground, the a/d no longer converts just a single voltage but rather the difference between two voltages. in these cases, the voltage on the selected + input is still sampled and held and therefore may be rapidly time varying just as in single- ended mode. however, the voltage on the selected C input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be performed accurately. the conversion time is 52 aclk cycles. therefore, a change in the C input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the C input this error would be: v error (max) = (v peak )(2 p)[ f(C)](52/f aclk ) where f(C) is the frequency of the C input voltage, v peak is its peak amplitude and f aclk is the frequency of the aclk. in most cases v error will not be significant. for a 60hz signal on the C input to generate a 0.25lsb error (300 m v) with the converter running at aclk = 4mhz, its peak value would have to be 61mv. 5. reference inputs the voltage between the reference inputs of the ltc1290 defines the voltage span of the a/d converter. the refer- ence inputs will have transient capacitive switching cur- rents due to the switched capacitor conversion technique (see figure 14). during each bit test of the conversion (every 4 aclk cycles), a capacitive current spike will be generated on the reference pins by the a/d. these current spikes settle quickly and do not cause a problem. how- ever, if slow settling circuitry is used to drive the reference inputs, care must be taken to insure that transients caused by these current spikes settle completely during each bit test of the conversion. figure 14. reference input equivalent circuit r on 8pf to 40pf ltc1290 ref+ r out v ref every 4 aclk cycles 14 13 ref ltc 1290 f14 when driving the reference inputs, two things should be kept in mind: 1. transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test (each 4 aclk cycles). figures 15 and 16 show examples of both adequate and poor settling. using a slower aclk will allow more time for the reference to settle. however, even at the maximum aclk rate of 4mhz most references and op amps can be made to settle within the 1 m s bit time. for example the lt1027 will settle adequately or with a 10 m f bypass capacitor at ref + the lt1021 can also be used. 2. it is recommended that ref C input be tied directly to the analog ground plane. if ref C is biased at a voltage other than ground, the voltage must not change during a conversion cycle. this voltage must also be free of noise and ripple with respect to analog ground. figure 16. poor reference settling can cause a/d errors horizontal: 1 m s/div vertical: 0.5mv/div figure 15. adequate reference settling horizontal: 1 m s/div vertical: 0.5mv/div
22 ltc1290 u s a o pp l ic at i wu u i for atio 6. reduced reference operation the effective resolution of the ltc1290 can be increased by reducing the input span of the converter. the ltc1290 exhibits good linearity and gain over a wide range of reference voltages (see the typical curves of linearity and gain error vs reference voltage). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. the following factors must be considered when operating at low v ref values: 1. offset 2. noise offset with reduced v ref the offset of the ltc1290 has a larger effect on the output code when the a/d is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of unadjusted offset error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 0.1mv which is 0.1lsb with a 5v reference becomes 0.4lsb with a 1.25v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the C input to the ltc1290. noise with reduced v ref the total input referred noise of the ltc1290 can be reduced to approximately 200 m v peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of noise error vs reference voltage shows the lsb contribution of this 200 m v of noise. for operation with a 5v reference, the 200 m v noise is only 0.16lsb peak-to-peak. in this case, the ltc1290 noise will contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1.25v reference, this same 200 m v noise is 0.64lsb peak-to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 0.64lsb. in this case averaging readings may be necessary. this noise data was taken in a very clean setup. any setup induced noise (noise or ripple on v cc , v ref , v in or v C ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup. 7. ltc1290 ac characteristics two commonly used figures of merit for specifying the dynamic performance of the a/ds in digital signal pro- cessing applications are the signal-to-noise ratio (snr) and the effective number of bits (enob). snr is defined as the ratio of the rms magnitude of the fundamental to the rms magnitude of all the nonfundamental signals up to the nyquist frequency (half the sampling frequency). the theoretical maximum snr for a sine wave input is given by: snr = (6.02n + 1.76db) where n is the number of bits. thus the snr is a function of the resolution of the a/d. for an ideal 12-bit a/d the snr is equal to 74db. a fast fourier transform(fft) plot of the output spectrum of the ltc1290 is shown in figures 17a and 17b. the input (f in ) frequencies are 1khz and 25khz with the sampling frequency (f s ) at 50.6khz. the snr obtained from the plot are 73.25db and 72.54db. rewriting the snr expression it is possible to obtain the equivalent resolution based on the snr measurement. n = (snr C 1.76db)/6.02 this is the so-called effective number of bits (enob). for the example shown in figures 17a and 17b, n = 11.9 bits and 11.8 bits, respectively. figure 18 shows a plot of enob as a function of input frequency. the curve shows the a/ds enob remain in the range of 11.9 to 11.8 for input frequencies up to f s /2. figure 19 shows an fft plot of the output spectrum for two tones applied to the input of the a/d. nonlinearities in the a/d will cause distortion products at the sum and differ- ence frequencies of the fundamentals and products of the
23 ltc1290 u s a o pp l ic at i wu u i for atio frequency (khz) 0 8 12 16 20 424 magnitude (db) 1290 ?f17a 0 ?0 ?0 ?0 ?0 100 120 140 f in = 1khz f sample = 50.6khz snr = 73.25db figure 17a. ltc1290 fft plot frequency (khz) 0 8 12 16 20 424 magnitude (db) 1290 ?f17b 0 ?0 ?0 ?0 ?0 100 120 140 f in = 25khz f sample = 50.6khz snr = 72.54db figure 17b. ltc1290 fft plot frequency (khz) 0 effective number of bits 80 1290 f18 20 40 100 12 11.6 11.2 10.8 10.4 10 9.6 9.2 8.8 60 f sample = 50.6khz figure 18. ltc1290 enob vs input frequency figure 19. ltc1290 fft plot frequency (khz) 0 8 12 16 20 424 magnitude (db) 1290 ?f19 0 ?0 ?0 ?0 ?0 100 120 f in1 = 5.1khz f in2 = 5.6khz f sample = 50.6khz fundamentals. this is classically referred to as intermodulation distortion (imd). 8. overvoltage protection applying signals to the analog mux that exceed the positive or negative supply of the device will degrade the accuracy of the a/d and possibly damage the device. for example this condition would occur if a signal is applied to the analog mux before power is applied to the ltc1290. another example is the input source is operating from different supplies of larger value than the ltc1290. these conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. as shown in figure 20, a 1k resistor is enough to stand off 15v (15ma for one only channel). if more than one channel exceeds the supplies then the following guidelines can be used. limit the current to 7ma per channel and 28ma for all channels. this means four channels can handle 7ma of input current each. reducing the aclk and sclk frequencies from the maximum of 4mhz and 2mhz, respectively, (see typical peformance characteristics curves maximum aclk fre- quency vs source resistance and sample-and-hold acquisition time vs source resistance) allows the use of figure 20. overvoltage protection for mux 5v 1290 f20 dgnd v agnd v cc 1k ltc1290 ch0 v in ?v 0.1 m f 22 m f
24 ltc1290 u s a o pp l ic at i wu u i for atio larger current limiting resistors. use 1n4148 diode clamps from the mux inputs to v cc and v C if the value of the series resistor will not allow the maximum clock speeds to be used or if an unknown source is used to drive the ltc1290 mux inputs. how the various power supplies to the ltc1290 are applied can also lead to overvoltage conditions. for single supply operation (i.e., unipolar mode), if v cc and ref + are not tied together, then v cc should be turned on first, then ref + . if this sequence cannot be met, connecting a diode from ref + to v cc is recommended (see figure 21). for dual supplies (bipolar mode) placing two schottky diodes from v cc and v C to ground (figure 23) will prevent power supply reversal from occuring when an input source is applied to the analog mux before power is applied to the device. power supply reversal occurs, for example, if the input is pulled below v C then v cc will pull a diode drop below ground which could cause the device not to power up properly. likewise, if the input is pulled above v cc then v C will be pulled a diode drop above ground. if no inputs are present on the mux, the schottky diodes are not required if v C is applied first, then v cc . because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device v cc without damaging the device. 5v 1290 f21 ref + v cc ltc1290 22 m f 1n4148 v ref 14 20 5v 1290 f22 dgnd v agnd v cc ltc1290 ?v 0.1 m f 22 m f 1n5817 1n5817 figure 21 figure 22. power supply reversal u s a o pp l ic at i ty p i ca l a quick look circuit for the ltc1290 users can get a quick look at the function and timing of the ltc1290 by using the following simple circuit. ref + and d in are tied to v cc selecting a 5v input span, ch7 as a single-ended input, unipolar mode, msb-first format and 16-bit word length. aclk and sclk are tied together and driven by an external clock. cs is driven at 1/128 the clock rate by the cd4520 and d out outputs the data. all other pins are tied to a ground plane. the output data from the d out pin can be viewed on an oscilloscope which is set up to trigger on the falling edge of cs. a quick look circuit for the ltc1290 1290 ta02 ltc1290 0.1 m f 22 m f f cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v in { to oscilloscope cd4520 clk en q1 q2 q3 q4 reset v ss v dd reset q4 q3 q2 q1 en clk clock in 2mhz max 5v v cc aclk sclk d in d out cs ref + ref v agnd f/128
25 ltc1290 u s a o pp l ic at i ty p i ca l scope trace of ltc1290 quick look circuit showing a/d output of 010101010101 (555 hex ) d out cs aclk/ sclk msb (b11) deglitcher time lsb (b0) fills zeros vertical: 5v/div horizontal: 1 m s/div sneak-a-bit tm the ltc1290s unique ability to software select the polar- ity of the differential inputs and the output word length is used to achieve one more bit of resolution. using the circuit below with two conversions and some software, a 2s complement 12-bit + sign word is returned to memory inside the mpu. the mc68hc05c4 was chosen as an example, however, any processor could be used. two 12-bit unipolar conversions are performed: the first over a 0v to 5v span and the second over a 0v to C5v span (by reversing the polarity of the inputs). the sign of the input is determined by which of the two spans contained it. then the resulting number (ranging from C4095 to +4095 decimal) is converted to 2s complement notation and stored in ram. sneak-a-bit circuit 1290 ta04 22 m f lt1021-5 mc68hc05c4 sclk mosi miso co ?v 0.1 m f 2mhz clock other channels or sneak-a-bit inputs v in 5v to 5v ltc1290 cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd 9v 5v 1st conversion (+) ch6 (? ch7 0v 0v 1st conversion 4096 steps 2nd conversion 4096 steps ?v 2nd conversion (? ch6 (+) ch7 0v v in v in v in 5v ?v software 8191 steps 1290 ta05 sneak-a-bit sneak-a-bit is a trademark of linear technology corp.
26 ltc1290 u s a o pp l ic at i ty p i ca l sneak-a-bit code for the ltc1290 using the mc68hc05c4 mnemonic description read C/+: lda #$3f load d in word for ltc1290 into acc jsr transfer read ltc1290 routine lda $60 load msbs from ltc1290 into acc sta $71 store msbs in $71 lda $61 load lsbs from ltc1290 into acc sta $72 store lsbs in $72 rts return read +/C: lda #$7f load d in word for ltc1290 into acc jsr transfer read ltc1290 routine lda $60 load msbs from ltc1290 into acc sta $73 store msbs in $73 lda $61 load lsbs from ltc1290 into acc sta $74 store lsbs in $74 rts return transfer: bclr 0,$02 cs goes low sta $0c load d in into spi, start transfer loop 1: tst $0b test status of spif bpl loop 1 loop to previous instruction if not done lda $0c load contents of spi data reg. into acc sta $0c start next cycle sta $60 store msbs in $60 loop 2: tst $0b test status of spif bpl loop 2 loop to previous instruction if not done bset 0,$02 cs goes high lda $0c load contents of spi data reg. into acc sta $61 store lsbs in $61 rts return chk sign: lda $73 load msbs of read into acc ora $74 or acc (msbs) with lsbs of read beq minus if result is 0 go to minus clc clear carry ror $73 rotate right $73 through carry ror $74 rotate right $74 through carry lda $73 load msbs of read into acc sta $77 store msbs in ram location $77 lda $74 load lsbs of read into acc sta $87 store lsbs in ram location $87 bra end go to end of routine minus: clc clear carry ror $71 shift msbs of read right ror $72 shift lsbs of read right com $71 1s complement of msbs com $72 1s complement of lsbs lda $72 load lsbs into acc add #$01 add 1 to lsbs sta $72 store acc in $72 clra clear acc adc $71 add with carry to msbs. result in acc sta $71 store acc in $71 sta $77 store msbs in ram location $77 lda $72 load lsbs in acc sta $87 store lsbs in ram location $87 end: rts return sneak-a-bit code d out from ltc1290 in mc68hc05c4 ram d in words for ltc1290 sign lsb mux addr. uni msbf word length d in 1 00 11 1111 d in 2 01 11 1111 d in 3 00 11 1111 (odd/sign) 1290 ta06 location $77 b12 b11 b10 b9 b8 b7 b6 b5 location $87 b4 b3 b2 b1 b0 filled with 0s sneak-a-bit code for the ltc1290 using the mc68hc05c4 mnemonic description lda #$50 configuration data for spcr sta $0a load configuration data into $0a lda #$ff configuration data for port c ddr sta $06 load configuration data into port c ddr bset 0,$02 make sure cs is high jsr read C/+ dummy read configures ltc1290 for next read jsr read C/+ read ch6 with respect to ch7 jsr read C/+ read ch7 with respect to ch6 jsr chk sign determines which reading has valid data, converts to 2s complement and stores in ram
27 ltc1290 u s a o pp l ic at i ty p i ca l power shutdown for battery-powered applications it is desirable to keep power dissipation at a minimum. the ltc1290 can be powered down when not in use reducing the supply current from a nominal value of 5ma to typically 5 m a (with aclk turned off). see the curve for supply current (power shutdown) vs aclk if aclk cannot be turned off when the ltc1290 is powered down. in this case the supply current is proportional to the aclk frequency and is independent of temperature until it reaches the magnitude of the supply current attained with aclk turned off. as an example of how to use this feature lets add this to the previous application, sneak-a-bit. after the chk sign subroutine call insert the following: ? ? jsr chk sign determines which reading has valid data, converts to 2s complement and stores in ram jsr shutdown ltc1290 power shutdown routine the actual subroutine is: shutdown: lda #$3d load d in word for ltc1290 into acc jsr transfer read ltc1290 routine rts return to place the device in power shutdown the word length bits are set to wl1 = 0 and wl0 = 1. the ltc1290 is powered up on the next request for a conversion and its ready to digitize an input signal immediately. power shutdown timing considerations after power shutdown has been requested, the ltc1290 is powered up on the next request for a conversion. this request can be initiated either by bringing cs low or by starting the next cycle of sclks if cs is kept low (see figures 3 and 4). when the sclk frequency is much slower than the aclk frequency a situation can arise where the ltc1290 could power down and then prema- turely power back up. power shutdown begins at the negative going edge of the 10th sclk once it has been requested. a dummy conversion is executed and the ltc1290 waits for the next request for conversion. if the sclks have not finished once the ltc1290 has finished its dummy conversion, it will recognize the next remaining sclks as a request to start a conversion and power up the ltc1290 (see figure 23). to prevent this, bring either cs high at the 10th sclk (figure 24) or clock out only 10 sclks (figure 25) when power shutdown is requested. 110 sclk cs power shutdown starts dummy conversion finishes after 52 aclk periods power up 1290 taf23 figure 23. power shutdown timing problem 110 sclk cs power shutdown starts dummy conversion finishes after 52 aclk periods power up 1290 taf24 figure 24. power shutdown timing 110 sclk cs power shutdown starts dummy conversion finishes after 52 aclk periods power up 1290 taf25 figure 25. power shutdown timing information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
28 ltc1290 1290fcs, sn1290 lt/gp 1098 2k rev c ? printed in usa ? linear technology corporation 1991 package descriptio u dimensions in inches (millimeters) unless otherwise noted. j package 20-lead cerdip (narrow 0.300, hermetic) (ltc dwg # 05-08-1110) 0.045 ?0.068 (1.143 ?1.727) full lead option 0.023 ?0.045 (0.584 ?1.143) half lead option corner leads option (4 plcs) 0.015 ?0.060 (0.381 ?1.524) 0.125 (3.175) min 0.014 ?0.026 (0.356 ?0.660) 0.045 ?0.068 (1.143 ?1.727) 0.100 0.010 (2.540 0.254) 0.200 (5.080) max 0 ?15 0.008 ?0.018 (0.203 ?0.457) 0.300 bsc (0.762 bsc) note: lead dimensions apply to solder dip/plate or tin plate leads j20 1197 3 7 56 10 9 1 4 28 11 20 16 15 17 14 13 12 19 18 0.005 (0.127) min 0.025 (0.635) rad typ 0.220 ?0.310 (5.588 ?7.874) 1.060 (26.924) max n package 20-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n20 1197 0.255 0.015* (6.477 0.381) 1.040* (26.416) max 1 2 34567 8 9 10 19 11 12 13 14 16 15 17 18 20 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) sw package 20-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** s20 (wide) 0396 0.496 ?0.512* (12.598 ?13.005) 20 19 18 17 16 15 14 13 0.394 ?0.419 (10.007 ?10.643) 11 12 12345678 10 9 note 1 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com part number description comments ltc1286/ltc1298 12-bit, micropower serial adc in so-8 1- or 2-channel, autoshutdown ltc1293/ltc1294/ltc1296 12-bit, multiplexed serial adc 6-, 8- or 8-channel with shutdown output ltc1594/ltc1598 12-bit, micropower serial adc 4- or 8-channel, 3v versions available related parts

▲Up To Search▲

Price & Availability of LTC1290DI

	To Download LTC1290DI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .